RTL Sign-off – At an Edge to become a Standard

Ever since I have seen Atrenta’s SpyGlass platform providing a comprehensive set of tools across the semiconductor design paradigm, I felt the need for a common set of standards to evolve …

Actived: 4 days ago


How to nail your PPA tradeoffs

The results show the design meets the 0.9 GHz timing target for both LVT libraries. Say you also want to include power in this analysis. Le points out to a case in which the results were …

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The Semiconductor Cycle Snowballs Down the Food.

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street July 2, 2022; Semiconductor Hard or Soft Landing? CHIPS Act? July 2, 2022; CHIPS for …

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Is Number of Signoff Corners an Issue

Semiconductor companies continue to use the traditional corner-based signoff approach that has been developed more than 40+ years ago and has since remained mainly unchanged as an …

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With Shrink Ending, What's Next

Jun 24, 2022. #26. Paul2 said: The planned expansion by 3 leading semi companies before the Russian invasion was in hundreds of billions of dollars over the term of …

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Jade Design Automation’s Register Management Tool

The software team may be working off of outdated information, wasting cycles on developing code that would need to be changed. Following is a real life example that Tamas …

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Verifying Inter-Chiplet Communication

The standard is also designed to support off-package connectivity, at board, rack or pod level, supported by retimers as needed. Scaling out is clearly a longer term goal. High …

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With Shrink Ending, What's Next

But now look at the density improvements each year, starting from 16nm A10 in 2016 (first one with an accurate gate count) -- x1.86, x1.69, x1.05, x1.54, x1.04.

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TSMC 2022 Technology Symposium Review – Process.

TSMC recently held their annual Technology Symposium in Santa Clara, CA. The presentations provided a comprehensive overview of their status and upcoming roadmap, …

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Intel Lands Top TSMC Customer

Intel. Intel Lands Top TSMC Customer. by Daniel Nenni on 07-25-2022 at 2:30 am. Categories: FinFET, Foundries, Intel. 12 Comments. Most people will be surprised by this but …

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Semiconductor Investments Won’t Pay Off if Congress Doesn’t Fix …

Semiconductor Investments Won’t Pay Off If Congress Doesn’t Fix the Talent Bottleneck. Including talent provisions in the final version of the House bill should be central to …

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TSMC Raises 2022 Outlook to 35%

TSMC's Q3 2022 revenue guidance is between US$19.8 ~ 20.6 billion. Let's assume the average US$20.2 billion as the Q3 2022 revenue. Estimated YoY growth rate …

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DUV, EUV now PUV Next gen Litho and Materials Shortages

DUV, EUV and now “PUV” to become next generation lithography. Lithography is the locomotive the pulls the entire semiconductor industry along the Moore’s Law curve to …

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The Five Biggest MCU Suppliers Accounted for 82% of 2021 Sales

The five largest microcontroller suppliers develop and sell ARM-based MCUs. These companies accounted for 82.1% of worldwide MCU sales in 2021 compared to 72.2% …

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The Semiconductor Market Downturn Has Started

What we alone said would surely happen, but what was widely denied by the industry, was confirmed with June’s WSTS Blue Book report. Right on cue with our December …

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Achieving Design Robustness in Signoff for Advanced Node

I had the opportunity to preview an upcoming webinar on SemiWiki that deals with design robustness for signoff regarding advanced node digital designs (think single-digit …

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SMIC Cut off by US Government is Doomsday Scenario for US …

Will likely lead to loss of all of China- 25% to 50% of revenues. Retaliation by China will worsen situation. SMIC cut off from US technology (Chip Equip) It has been …

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Standardization of Chiplet Models for Heterogeneous

The emergence of 2.5D packaging technology for heterogeneous die integration offers significant benefits to system architects. Functional units may be implemented using …

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